IBM’s 0.7 nm Nanostack Still Needs Someone Else’s Fab

IBM said on June 25, 2026 that its nanostack process can pack nearly 100 billion transistors on a fingernail-sized die. The company billed the work as the world’s first sub-1 nanometer chip technology, at a 0.7 nm, or 7 angstrom, node built in Albany, New York.

The hardware on the wafer is a research vehicle. IBM showed a working CMOS inverter and a stacked-transistor flow it says foundry partners could put into production as early as the next five years.

The Lab Built an Inverter, Not a Product

Jay Gambetta, director of IBM Research and IBM Fellow, called the result a leap past ordinary shrinks. Huiming Bu, vice president of IBM Semiconductors Global R&D, told a briefing that nanosheet transistors are already the base for leading 3 nm and 2 nm foundry processes, and that nanostack is meant to replace them.

What the Albany line actually proved is narrower than a shipping processor. IBM says the architecture was checked with ultra-thin dielectric bonding in a CMOS flow, dual-channel engineering across the stacked devices, and a CMOS inverter that switched as expected. Those three tests are how the company argues the stack can be built and can compute.

WHAT ALBANY ACTUALLY SHOWED

• Dielectric bond: Ultra-thin bonding joins two nanosheet device layers in a CMOS integration flow.
• Dual channels: Top and bottom devices can be engineered separately, including different materials in each layer.
• CMOS inverter: A working inverter demonstrated switching performance in line with the design.
• SRAM paper: A VLSI 2026 study reported 40 percent scaling in staggered-channel SRAM bit cells.

S. Reboh and colleagues described the transistor stack at the 2025 Symposium on VLSI Technology and Circuits as sequential nanosheet-on-nanosheet CMOS, with a thermally stable bottom gate and thin dielectric isolation. Chen Zhang and colleagues followed at VLSI 2026 with the SRAM result. The June 2026 news release sits on those papers, not on a CPU that leaves a factory.

Why 0.7 nm Does Not Mean 0.7 nm

IBM’s own release says transistor nodes now name a manufacturing generation rather than a physical feature size. Qing Cao, a materials science professor at the University of Illinois Urbana-Champaign who was not part of the work, put it more bluntly: 0.7 nm is a marketing label. He said the distance between transistors has been stuck near 40 nm for a long time.

The pieces you can measure are coarser than the node name. Each stacked transistor uses three nanosheets about 5 nm thick, roughly 15 atoms of silicon, with about 9 nm between sheets. Analyst Ian Cutress, who in 2021 got IBM to treat a “fingernail” as about 150 square millimeters, puts the 2021 2 nm density at 333 million transistors per square millimeter and the new claim at 666 million on the same area.

On May 6, 2021, IBM said its 2 nm nanosheet test chip could fit 50 billion transistors on a fingernail. That older node was projected to deliver about 45 percent more performance, or 75 percent lower energy use, than 7 nm chips. Nanostack’s published figures are a different comparison: up to 50 percent more performance, or 70 percent better energy efficiency, than IBM’s 2 nm node, as alternative operating points, not both at once.

Reading 0.7 nm as a gap the width of an atom misses the convention the industry has used for years. The number is a generation tag. The stack is the actual change.

Transistors Sit in Two Staggered Layers

Nanostack is IBM’s name for a complementary field-effect transistor, or CFET, built by sequential wafer stacking. One layer of nanosheet devices is finished, another is bonded on top, and the two are wired into CMOS pairs. IBM staggers the upper devices instead of parking them directly above the lower ones, which it says opens contacts and simplifies wiring.

Intel, Samsung, TSMC, and imec have all published CFET work. IBM’s distinction is the offset sequential stack, which lets n-type and p-type devices use different materials and silicon orientations. The VLSI 2025 paper projects that 4-track base cells can deliver about 50 percent logic area scaling versus IBM’s 2 nm node, alongside the 50 percent iso-power speed gain or 70 percent iso-performance power cut.

Cao warned that a second tier raises the fail rate, because a defect in either layer kills the whole die, and that the top devices have to be finished without melting the layer below. He said that thermal budget sits near 400 °C. IBM has not published the low-temperature trick it used for the second stack.

Dan Hutcheson, vice chair of the analysis firm TechInsights, called the direction transformational and said it puts another 10, 15 years on the roadmap. IBM’s release is more cautious: at least a decade of further scaling if the stack holds.

Rapidus Is Still Ramping IBM’s 2 nm Recipe

IBM sold its last merchant fab years ago. Process research in Albany is licensed. Rapidus in Japan and Samsung in South Korea took earlier IBM nodes. IBM declined to name a foundry that would take nanostack into volume.

Rapidus is the live test of that model. The Japanese foundry licensed IBM’s 2 nm gate-all-around flow in December 2022 and has been training engineers at Albany NanoTech. President Atsuyoshi Koike said in early October 2026 that more than 160 Rapidus engineers had been sent to Albany, that more than 100 were already back at the IIM-1 plant in Chitose, Hokkaido, and that 2 nm mass production remains aimed at 2027.

While IBM talks about 0.7 nm, the 2 nm chips that TSMC already sells are in factories. TSMC’s process pages say its nanosheet N2 high-volume manufacturing in 2025 began in the fourth quarter, with a 2026 ramp for phones and high-performance computing.

WHERE THE DENSITY CLAIM MEETS A FACTORY

Five years after IBM’s last “world’s first” node, the company that paid for that recipe is still chasing yield in Hokkaido. Nanostack now asks a foundry to do the same climb one architecture later, with wafer bonding and a staggered CFET in the mix.

SRAM Cell Height Falls 40 Percent

The AI pitch is not the transistor headline. It is on-chip memory. IBM says a staggered-channel layout cuts the height of a six-transistor SRAM bit cell by 40 percent, which is the same 40 percent SRAM scaling reported at VLSI 2026.

Gambetta said SRAM barely moved from the 3 nm generation to 2 nm, improving only a few percent. Caches are where AI accelerators stall when weights and activations cannot sit next to the math units. A 40 percent cell-height cut is the figure chip designers would actually spend money on, if a foundry can print it at yield.

Bu framed the power side in one line: everyone wants more performance, but no one wants to pay the bill for the power. The 70 percent efficiency number is the version of nanostack that holds speed still and spends less energy. The 50 percent performance number is the version that spends the same energy and runs faster. Designers pick one corner, not both.

High-NA EUV Comes to Albany After the Demo

IBM and partners including Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions are building High numerical aperture extreme ultraviolet processes around an ASML scanner that NY Creates is installing at Albany NanoTech. IBM said that tool is essential for later logic scaling and that the partners have already made working devices with new High-NA flows.

First major modules of the scanner reached Albany in July 2026, weeks after the nanostack release. NY Creates said initial development milestones are expected by the end of 2026, with the system supporting research in early 2027. Gambetta tied the two events together: nanostack was developed on that campus, and High-NA is the next printing step.

THE CLOCK FROM DEMO TO TOOLING

1. May 6, 2021: IBM shows a 2 nm nanosheet test chip with 50 billion transistors at Albany NanoTech.
2. December 2022: Rapidus signs on to license IBM’s 2 nm gate-all-around process.
3. June 8, 2025: Reboh and colleagues present NanoStack for a CMOS 7A node at VLSI.
4. July 2025: Rapidus reports 2 nm GAA transistor operation on its Chitose pilot line.
5. June 25, 2026: IBM publicly names nanostack as sub-1 nm chip technology.
6. July 2026: First High-NA EUV modules arrive at Albany NanoTech.
7. Early 2027: High-NA is expected to start supporting research; Rapidus still aims at 2 nm volume later that year.

Cutress noted that High-NA is helpful for cutting the number of patterning steps, not a hard requirement for the stack itself. The harder software problem is design tools that treat the vertical direction as a first-class axis. IBM has said EDA houses have to treat 3D at transistor level the way they already treat 3D packaging, and that this enablement is part of the five-year clock.

A Five-Year Path Runs Through Other Fabs

IBM’s written path is production as early as the next five years, which from the June 2026 release lands around 2031. Bu told reporters commercial chips could start that early and would more likely become mainstream inside a decade, across CPUs and GPUs, if foundries adopt the stack.

Gambetta said he expects nanostack chips to show up widely in data centers within a decade, where the efficiency gain would hit power bills. He also said the 40 percent SRAM result will eventually show up in AI workflows that need bandwidth and efficiency together.

IBM’s latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms. With our new nanostack architecture, we’re not just making smaller transistors, we’re reinventing how chips are built to deliver dramatically more power and energy efficiency.

Jay Gambetta, Director of IBM Research and IBM Fellow, IBM announcement, June 25, 2026

The sentence that ages better is Bu’s other one. IBM will not be the factory. The 0.7 nm stack has to survive bonding yield, a 400 °C thermal budget, High-NA process work, and a design-kit that does not yet exist as a production PDK. Rapidus is still trying to turn IBM’s 2 nm paper into wafers people will buy. Until a named foundry puts nanostack on a process design kit, the sub-1 nm chip is a bonded inverter and a density claim waiting on someone else’s line.