Cadence Pushes Agentic AI Into Chip Design at COMPUTEX 2026

Cadence told a packed COMPUTEX forum in Taipei on June 4 that agentic AI is moving from chip design experiments into production tapeouts. Multi-agent systems are now writing RTL, running verification, and routing blocks at Nvidia, Altera, and Tenstorrent. The talk, titled “Pioneering the Future of IC with Agentic AI,” is Cadence’s clearest public roadmap yet for putting AI inside every step of the chip design loop. The product of that roadmap is already running in customer flows. The work that pulled it forward is AI’s own appetite for custom silicon.

Dr. Paul Cunningham, SVP and General Manager of the System Verification Group at Cadence Design Systems, used his 25-minute slot to argue that the industry has run out of the abstractions it can lean on. “The need and the desire to just shrink the schedules is also like it never has been before,” he said, citing the gap between AI model release cadences and chip development timelines. The next layer of design productivity has to come from something other than faster engineers, in his framing. That something is the same AI Cadence is now embedding inside EDA. The result, he argued, is a chip design loop in which the machine writes a chunk of the chip, checks it, and routes it before a human touches it.

The Talk That Named the Problem

Cadence’s forum session ran from 11:30 to 11:55 a.m. on June 4 at TaiNEX 2, room 701BF in Taipei, slotted into the COMPUTEX 2026 forum schedule in Taipei’s Gen AI and Intelligent Content Applications track. Synopsys VP of AI and Machine Learning Thomas Andersen ran a parallel session in the same track that morning titled “Automating Chip Design with AgentEngineer Technology.” Texas Instruments VP and head of R&D Jeff Morroni filled an adjacent slot on AI data-center power design. Cunningham’s session was the one that mapped the full chip-design surface, from front-end RTL through signoff.

His framing was blunt. “The need and the desire to just shrink the schedules is also like it never has been before,” Cunningham said, pointing to the mismatch between AI model release cadences and silicon timelines. New AI foundation models are emerging every few months. Advanced processors can require two years or more from architecture definition to production. That is the calendar gap the agentic push is meant to close, and the only way it closes is by handing the routine work to AI.

Cadence acquired Seattle-based ChipStack in November 2025 and shipped the ChipStack AI Super Agent four months later as the front-end piece of a broader agentic portfolio. That portfolio now also includes InnoStack for digital implementation and ViraStack for analog design. The COMPUTEX forum was the venue where Cunningham lined up the three stacks alongside the AgentStack orchestrator and the JedAI enterprise middleware. Customers running the first stack in production today include Nvidia, Altera, and Tenstorrent.

Three Stages, From Optimization to Autonomy

Cunningham organized Cadence’s AI work into three buckets, each adding a layer of automation engineers did not have before. The earliest, optimization AI, has been running in customer flows for years. The latest, agentic AI, is what the COMPUTEX talk was built around.

The three layers Cadence is now stacking on top of each other:

• Optimization AI: specialized neural networks, often pre-LLM, built for one engineering job. Cerebrus, Cadence’s digital implementation optimizer, has explored thousands of design options since its launch to hit power, performance, and area tradeoffs, and has expanded from single blocks to full system-on-chip optimization with cross-generation learning.
• Conversational AI: natural-language front ends sitting on top of EDA tools, so engineers describe an objective and let the software drive scripts, runs, and analyses. Engineers still direct the work.
• Agentic AI: multi-step systems that plan, iterate, validate, and run on their own. ChipStack, InnoStack, and ViraStack sit at this tier, with AgentStack orchestrating them across front-end, implementation, and analog flows.

Cunningham was careful to point out that the older layers are not being retired. Custom machine-learning models have cut verification compute by factors of five to twenty, he said, while staying inside the engineering rigor the work demands. Cerebrus, in production for several years, is still in the same product line as ChipStack.

What Each Agent Stack Actually Runs

Cadence’s agentic bet lands on three named products, each pointed at a different stage of chip development. Together they cover the path from spec to signoff, as laid out in the Full coverage of Cunningham’s COMPUTEX 2026 talk. The fourth product in the family, AgentStack, orchestrates them.

ChipStack has the most production mileage. Cadence’s own design IP organization used it on a PCIe 7 controller project whose specification ran past 6,000 pages; the system generated substantial portions of the design and verification environment, and the project hit what Cunningham described as approximately a twofold schedule improvement. Customer deployments stretch to Nvidia, Altera, and Tenstorrent. Altera says it has seen more than 10x performance improvement on its flagship FPGA projects. Tenstorrent reports up to 4x reduction in formal verification time across three critical design blocks during a three-month evaluation, with Cadence’s Level-5 ChipStack verification turnaround separately documented in weeks-to-days results. The customer detail comes from ChipStack’s customer rollout and engineering detail.

InnoStack and ViraStack are earlier. Both are in beta testing with development partners, per the EDN Asia coverage of Cunningham’s talk. InnoStack targets congestion, routing, timing, and power integrity in the back end, while ViraStack is aimed at analog and custom work including schematic generation, layout development, and physical implementation.

Underneath all three sits AgentStack, the orchestrator that gives them a common terminal interface and lets them share knowledge and skills across domains. Enterprise rollouts run through JedAI, a middleware platform Cadence introduced to manage model access, security policies, authentication, telemetry, and cost controls for both cloud frontier models and on-premises open-weight ones. As agents spread across engineering teams, Cunningham said, that enterprise layer stops being optional. The data, the model governance, and the cost controls all live there.

Why AI in EDA, and Why Right Now

The trigger for the agentic push is not Cadence’s product roadmap. It is the demand curve AI has put on the chip industry itself. Semiconductor geometries are now approaching the 14-angstrom to 10-angstrom range. Multi-die packaging is integrating dozens of dies per package through advanced interposers and 3D stacking.

Packages containing several trillion transistors could become commonplace before the end of the decade, Cunningham said, and AI is the engine pulling the curve. On top of that physical pressure sits a calendar problem. New AI foundation models ship every few months while advanced processors can require two years or more from architecture definition to production.

Cunningham’s prescription is a return to two moves the industry has used before. The first is higher abstraction: design flows that start from a natural-language architecture specification, with AI systems translating the requirements into implementations the way synthesis once translated Verilog and VHDL into gates. The second is broader reuse: agentic systems that automate debugging, analysis, design exploration, verification, and optimization so engineering effort flows to higher-value decisions. Both moves are pulled forward by the same force: data center buildouts today, autonomous vehicles and humanoid robots tomorrow, all of them waiting on silicon that does not yet exist. The bottleneck for that silicon, on Cunningham’s account, is the design cycle itself.

Why Generic LLMs Cannot Do the Job Alone

Cunningham pushed back on the idea that a frontier large language model, dropped into chip design as-is, would close the productivity gap. Chip work involves millions of tokens of structured information running through highly specialized workflows, and a raw model drifts off-spec fast. The answer, in his framing, is scaffolding. The scaffolding has to break the work into steps and wrap each step with grounded tools.

You really need to create quite a complex flow or a scaffold to divide and conquer the problem, to break it up into a series of steps to guardrail the LLM process.

Cunningham, speaking at the COMPUTEX 2026 forum as Cadence’s SVP and GM of the System Verification Group, framed that scaffolding as the load-bearing piece of any agentic EDA workflow. Cadence has spent 30 or 40 years building grounded EDA tools that analyze, assess, check, and explore, and the agentic systems sit on top of those, iterating with them and leaving the older tools in place. The agentic vocabulary, skills, scaffolding, knowledge graphs, is largely new packaging for older EDA ideas.

ChipStack’s specific fix is what Cadence calls a mental model. Matt Graham, senior group director of Verification Software Product Management at Cadence, told EE Times that the mental model turns a vanilla LLM into a chip designer by giving it a structured representation of the design and specification. Kartik Hegde, senior group director of Agentic AI and ChipStack, said the team measured the difference. Turn the mental model off and accuracy on verification tasks drops by 30 to 40 percent. Turn it back on and the agent stays grounded against the source of truth.

Synopsys’ Counter-Bet in the Same Week

Cadence is not the only EDA vendor with an agentic story. Synopsys fielded its own session at COMPUTEX on June 4, with VP of AI and Machine Learning Thomas Andersen presenting “Automating Chip Design with AgentEngineer Technology.” Synopsys frames its work as an L1 to L5 autonomy ladder, climbing from assistive automation up to fully self-directed agents. Cadence and Synopsys overlap on the headline promise: autonomous execution of engineering tasks, multi-agent collaboration, and a human-AI partnership where engineers keep strategic control.

The two vendors are converging on the same destination: autonomous chip design with humans in strategic control. Cadence arrived there through acquisition, with the November 2025 buyout of Seattle-based ChipStack as the keystone. Synopsys built its way there through in-house development of the AgentEngineer framework and an L1 to L5 ladder. Cadence leans on the mental-model knowledge graph as its defense against LLM hallucination in chip work. Synopsys leans on staged autonomy, with each rung earning the right to the next.

Where Human Engineers Stay in the Loop

The agentic pitch keeps human chip designers in the loop but pushes them up the stack. Hamid Shojaei, CTO and co-founder of ChipStack, told EE Times that the platform reads the design plan, codes, runs, and debugs, while engineers stay in control by inspecting each generated step and feeding in feedback. Cadence positions the work as Level 4 automation on its own autonomy ladder, with Level 5 reserved for fully self-directed design. Full autonomy across an end-to-end tapeout is still on the road, not on the production floor.

What stays human, by Cunningham’s own framing, is the higher-value decision: where to spend engineering attention, which tradeoffs to take, which architectural directions to pursue. What moves to the agent is the mechanical workload: writing RTL from spec, generating UVM testbenches, running regressions, triaging failures, mining analog IP libraries for migration candidates. Engineers still own the parts that require judgment and taste. They cede the parts that scale with compute, leaving the insight-driven parts to humans. The design loop shifts up the value stack even as the silicon stays the same.

Engineering retraining, model governance, and the calibration of trust between human reviewers and AI agents all draw on the same schedule Cadence and Synopsys are trying to compress. Neither vendor has disclosed what those costs add up to in headcount or dollars. Whether the productivity gains outrun those costs inside the two-year window AI itself is forcing on the chip industry is the question both vendors’ roadmaps will be judged against.

Frequently Asked Questions

What is agentic AI in chip design?

Agentic AI in chip design refers to multi-step AI systems that can plan, iterate, and validate engineering tasks across an electronic design automation (EDA) flow with limited human input. Unlike conversational AI assistants that respond to a single prompt, agentic systems break complex objectives into sub-tasks and invoke grounded EDA tools to complete them.

Who is Paul Cunningham and what did he announce at COMPUTEX 2026?

Dr. Paul Cunningham is Senior Vice President and General Manager of the System Verification Group at Cadence Design Systems. At COMPUTEX 2026 in Taipei on June 4, he presented “Pioneering the Future of IC with Agentic AI,” laying out Cadence’s roadmap for layering AI agents across the chip design flow from optimization and conversational tools through autonomous ChipStack, InnoStack, and ViraStack systems.

What is Cadence ChipStack and which companies use it?

ChipStack is Cadence’s agentic AI platform for digital front-end design and verification, acquired with Seattle-based ChipStack in November 2025. It is in production at Nvidia, Altera, and Tenstorrent. Altera reports more than 10x performance improvement on flagship FPGA projects. Tenstorrent reports up to 4x reduction in formal verification time across three critical design blocks in a three-month evaluation.

How does Cadence’s agentic AI compare to Synopsys’ AgentEngineer?

Cadence and Synopsys both pitch multi-agent systems that automate chip design tasks while keeping engineers in strategic control. Cadence’s ChipStack is differentiated by its mental model knowledge graph, which grounds every agent against a structured specification and shaves 30 to 40 percent off hallucination-driven verification errors in Cadence’s own testing. Synopsys frames its competing AgentEngineer technology as an L1 to L5 autonomy ladder, with Level 5 representing fully self-directed design that no human steers.

What is the mental model in Cadence’s ChipStack?

A mental model is a structured knowledge representation that aggregates design data, specifications, diagrams, libraries, and other human-readable content describing a chip’s design intent. ChipStack uses it as a persistent source of truth that all downstream agents refer back to. Cadence’s own measurement, run by turning the mental model on and off in head-to-head verification tasks, shows that the mental model adds 30 to 40 percent accuracy on those tasks.