Cadence’s Level-5 AI Chip Design Agent Cuts Verification From 5 Weeks to 1 Day

Cadence used COMPUTEX 2026 to unveil a fully autonomous AI design engineer for chip verification, the first the semiconductor industry has shipped. The new Level-5 build of the ChipStack AI Super Agent, run on NVIDIA Nemotron models inside the NVIDIA OpenShell runtime, compresses a five-week verification loop to less than a day and delivers over 40x faster RTL validation cycles than the current Cadence workflow.

The announcement lands a week after Synopsys said it had demonstrated the first Level-4 multi-agent workflow for chip design at its own Converge 2026 event, and it lands five months after Cadence closed its November 2025 acquisition of Seattle-based ChipStack. It pushes EDA, a market variously sized at roughly $15 billion to $20 billion a year and long run by a Cadence-Synopsys-Siemens oligopoly, to the front edge of the autonomous-agent race in engineering software.

Cadence Hands Chip Verification to a Level-5 AI Agent

Cadence’s announcement, dated May 31 from San Jose and timed to NVIDIA CEO Jensen Huang’s Computex keynote in Taipei, extends the ChipStack AI Super Agent to Level-5 autonomy. The February 2026 version still required engineers to walk the agent through the workflow step by step. The Level-5 build evaluates intermediate results on its own, picks the next action, and iterates toward closure across specification analysis, RTL generation, verification planning, formal analysis, simulation, debugging, and design convergence.

Cadence framed the jump in plain terms. The agent moves from a copilot that drafts a piece of RTL or a testbench to a virtual engineer that can take a spec, run the design and verification loop, and come back with a working result, with humans able to inspect, guide, and step in at any point.

We’re taking the next step, moving from AI that assists engineers to autonomous virtual engineers that can implement real design and verification work, grounded in our signoff-accurate engines and running in secure, governed environments so teams can innovate faster with confidence.

That is Paul Cunningham, senior vice president and general manager of the System Verification Group at Cadence, in the company’s announcement. Timothy Costa, vice president and general manager of computational engineering at NVIDIA, added the security framing the customer base is going to want to hear: By securing Cadence’s ChipStack AI Super Agent with NVIDIA OpenShell and powering it with Nemotron models, Cadence is bringing governed autonomy to chip design workflows, giving customers a faster, more secure path to develop and validate advanced semiconductors.

The Numbers Behind the Five-Week-to-One-Day Claim

Three numbers anchor the announcement, and the smallest of them is the most consequential.

First, the speedup. Cadence says the new agent runs RTL validation cycles more than 40x faster than its existing workflow. Second, the loop time. A verification process that traditionally takes five weeks now completes in less than a day in leading-edge deployments, the company says. Third, the scale at which it was tested. At NVIDIA, thousands of verification engineers collectively consume billions of compute hours a year to run millions of tests on chip designs, and the new agent lets each engineer launch hundreds of dynamic simulations through Cadence Xcelium Logic Simulation and Jasper Formal Verification.

Those numbers are not coming out of nowhere. In February, Cadence announced the first ChipStack-based product and quoted roughly 10x productivity gains on RTL and testbench work. The June number is a 4x jump on top of that, layered on the same workflow in four months. Forbes reported the gap in starker terms, noting that the new agent orchestrated the equivalent of thousands of engineers and millions of verification tests in the loop Jensen Huang showed on the Computex stage. Cadence declined to break out how much of the 40x comes from agentic orchestration versus running Xcelium and Jasper in parallel versus the underlying GPU acceleration; the company said only that all three contribute.

One figure that did not get quoted at Computex is worth flagging. Nvidia’s own engineers, Huang said on stage, have already started working with Cadence’s virtual engineers inside Slack channels, and have used them to convert codebases in five hours that would have taken ten engineers a year to rewrite. That anecdote is from the April CadenceLIVE keynote, reported by Moor Insights, not the May 31 release. Cadence did not include it in its Computex materials.

Why NVIDIA’s OpenShell and Nemotron Sit Underneath

The Level-5 agent is not a Cadence model in isolation. It is a Cadence orchestration layer, sitting on top of NVIDIA’s Nemotron family of reasoning models, running inside a sandboxed runtime called NVIDIA OpenShell that the chip company has been building for production-grade autonomous agents.

Nemotron is the engine that decides what the agent should try next. OpenShell is the box it runs in, and the box matters because chip companies do not want a generic LLM wandering around a database of unreleased RTL, foundry PDKs, or customer IP. OpenShell enforces policy controls, isolates the agent from the rest of the customer’s infrastructure, and gates access to design data, internal tools, and compute. Cadence says the agent’s behavior is also tightly coupled to its own physics-based signoff engines, so AI-driven decisions are checked against the same computational models the company’s regular tools use to declare a chip ready for tape-out.

There is a strategic read here that does not fit on a slide. The product Cadence is selling includes, baked in, a model layer (Nemotron) and a runtime layer (OpenShell) that both come from its largest customer and most powerful partner. NVIDIA also disclosed at Computex that it is an early deployment partner for Cadence’s new AgentStack framework, meaning NVIDIA is both the supplier of the agent’s brain and an early customer of the agent itself. The agent is also compatible with OpenAI Codex and Anthropic’s Claude Code, the company said, so engineering teams can drive it from the development environments they already use.

From ChipStack Acquisition to a Full Agent Stack in Eight Months

Eight months ago, Cadence did not have an agentic product. Today it has four super agents and an orchestration layer, with a fifth on the way. The build-out reads as a deliberate sequence, not a string of demos.

• November 2025: Cadence signs a definitive agreement to acquire Seattle-based ChipStack, a startup whose generative-AI product was already accelerating formal and simulation-based verification by more than 70% at customer sites. The deal closes that quarter.
• February 2026: Cadence ships the first ChipStack-based product, the ChipStack AI Super Agent, focused on front-end RTL generation and verification. Early customers include Altera, Google Cloud, MediaTek, NVIDIA, Qualcomm, and Tenstorrent, per Moor Insights reporting from CadenceLIVE.
• April 2026, CadenceLIVE Silicon Valley: Cadence expands into a portfolio. ViraStack AI Super Agent covers custom and analog design. InnoStack AI Super Agent handles digital implementation and signoff. AgentStack debuts as the orchestration framework that coordinates multiple super agents across the design stack. Moor Insights also reports 3DStack and SystemStack for 3D-IC and multiphysics work, though the company’s own AI overview page lists the first three alongside ChipStack as the headline agents.
• May 31, 2026, COMPUTEX Taipei: ChipStack reaches Level-5 autonomy, the first autonomous virtual engineer in the EDA stack, with early access in the second half of 2026.

Two things stand out about that timeline. First, the cadence is faster than typical EDA shipping, where new product generations tend to span years, not quarters. Second, almost every step has been co-announced with NVIDIA. Cadence is not just building on NVIDIA’s runtime; it is releasing products in lockstep with NVIDIA’s biggest on-stage moments.

What the Verification Engineer Actually Does Now

The 40x number and the sub-day loop get the headlines, but the second-order shift is in the job. Cadence says its customers’ expert engineers will take on more ambitious silicon designs with greater speed and confidence. The press release uses a more telling phrase: this shifts engineers from executing individual tasks to supervising outcomes and guiding intent.

In practice, that means the verification engineer who used to write the testbench, kick off the regression, watch the logs, and triage the failure is now the engineer who defines what closure looks like, reviews the agent’s plan, and signs off on the result. The labor model changes in two directions at once. Senior engineers get more leverage, but they also lose the daily contact with the failure modes that built their judgment. Junior engineers, who used to learn the craft by handling the babysitting work, now have to learn it by supervising an agent that handles the babysitting for them.

Forbes’s Karl Freund, who covered the Computex demonstration, framed the trade this way: Will this eliminate electronic design jobs? Hardly. They will move up the stack, allowing senior design engineers to focus on what they do best, and greatly reduce the part of the job they hate the most: boring babysitting of various design tools as they churn away for hours. The piece also notes the risk in the same breath. Junior engineers learn the trade faster, but they learn it differently, and the institutional memory of how a chip fails lives in the part of the workflow the agent is replacing.

The Trust and IP Questions Still Unresolved

Cadence is selling this as production-grade. The customers who pay for it will want to know what production-grade means in practice.

Cadence’s answer is the coupling to its signoff engines. The agent does not get to declare a design done; the physics-based tools underneath do. That is the trust mechanism. The second mechanism is the OpenShell sandbox, which limits what data the agent can see and what actions it can take. Neither mechanism is new; what is new is putting them in front of an agent that now plans, decides, and iterates without a human in the loop on every step.

Three questions are still open. First, audit. When a fully autonomous verification loop passes a design that later turns out to be wrong, who is on the hook? Cadence says the engineer still reviews and signs off, but the practical signoff is going to be faster and shallower, and customers will need a paper trail that survives an incident. Second, IP. OpenShell isolates the agent from the customer’s network, but the Nemotron model that drives the agent is, in some form, shared infrastructure. Chip companies working on unreleased architectures will want to know exactly which model weights see which prompts, and how that data is logged. Third, scope. Level-5 autonomy here is scoped to verification, not to the whole design flow. Cadence is going to widen the scope, and the trust questions widen with it.

Synopsys Says It Got Here First

Cadence calls itself the first fully autonomous virtual engineer in semiconductors. Synopsys called itself the first L4 orchestrated, multi-agent, adaptive learning workflow for chip design when it demonstrated the system at Synopsys Converge 2026 in Santa Clara on March 11. Both companies are using the same industry agentic-autonomy ladder, and they are claiming different rungs.

The competitive picture looks like this:

The first-to-market race matters because the EDA market pays for productivity, and the productivity story is now an autonomy story. Cadence’s press release is dated May 31. Synopsys’s demonstration is dated March 11. Both companies, in their own materials, are calling their announcement the industry’s first of its kind, at their respective autonomy level. The contest is over how many steps the agent takes without a human in the loop, and over which vendor’s customers hit production first.

Cadence said the Level-5 capabilities of ChipStack and the AgentStack orchestration framework will be available to early-access customers in the second half of 2026, with broader availability to follow. Synopsys has not yet named a general-availability date for its L4 workflow. The two rollouts will run in parallel through 2026, and the chip companies buying EDA tools will be the ones deciding which autonomy level actually holds up in production. Cadence’s ChipStack AI Super Agent product page is live; the full announcement, including the complete May 31 press release and Cunningham and Costa quotes, is mirrored on StockTitan. Independent analysis from Moor Insights on the broader agentic stack fills in the customer names and the CadenceLIVE context.

Inside the larger NVIDIA partnership story, the move tracks with two other recent deals on similar terms. NVIDIA and SK Hynix signed a multiyear co-design pact in Seoul to align AI memory with Vera Rubin and RTX Spark, and NVIDIA and LG Group built a six-subsidiary AI factory deal around NVIDIA Cosmos for robotics training data. The Cadence arrangement is the same shape: NVIDIA supplies the platform underneath, the partner company supplies the domain workflow, and the joint claim is a productivity jump that neither could deliver alone.