Samsung and SK Hynix Chase a Memory Bet That Analysts Called Dead

Samsung Electronics and SK hynix are racing into a memory category that a prominent chip analysis firm declared dead for artificial intelligence less than a year ago. Both Korean chipmakers are now shipping test hardware and publishing benchmark data on Compute Express Link (CXL), a standard that lets a server reach a deep pool of memory without buying more processors just to hold it. SK hynix showed a 256 gigabyte version of its module in Las Vegas in June. Samsung said on July 9 that a terabyte scale CXL memory pool hit about 92 percent of DRAM level inference speed across eight GPUs.

The timing cuts both ways. Three days before that benchmark, industry sources said Samsung’s next CXL generation had already slipped because Intel and AMD have not shipped the server chips it depends on. Nvidia, the industry’s dominant chipmaker, is meanwhile building its own rival memory shortcut instead of leaning only on the open standard.

Two Ceilings and One Capacity Wall

The problem CXL is meant to solve has nothing to do with speed. It is capacity, and where a chip can and cannot reach it.

In a typical AI server, high bandwidth memory (HBM) sits stacked next to the graphics processor, and ordinary DRAM sits next to the central processor. Neither pool can grow on its own. Each is soldered or slotted to the one chip it serves, so adding memory usually means adding another expensive processor just to carry it.

CXL breaks that link. It rides over the same PCIe interface used for other add in cards, sitting between conventional DRAM and solid state storage in speed, but offering far more room than anything wired directly to a chip. A server can reach a large shared memory pool without buying more compute to hold it.

That appeal has grown as large language model inference builds up a growing store of session data, known as the key value cache. Once that cache outgrows available memory, systems slow down or repeat work already finished. Samsung and SK hynix are chasing this new category while their own shares still swing hard; Korea’s market recently beat its 2008 volatility record with the two memory makers at the center of the moves.

The Chip Analysts Who Called CXL Dead

Less than a year ago, the wager looked much shakier. SemiAnalysis, a widely read semiconductor industry analysis firm, published a piece in October 2025 arguing that CXL had largely failed to find a home in AI infrastructure. The firm said many hyperscalers and large chip companies had quietly shelved CXL projects after chasing the standard hard just two years earlier.

Its technical case centered on bandwidth. CXL rides on PCIe, and PCIe’s underlying signaling technology was, by the firm’s estimate, roughly three times less efficient than the proprietary and Ethernet based links AI clusters actually use to scale compute up and out. SemiAnalysis argued that gap would persist even as the industry moved to PCIe 6.0, keeping CXL out of the scale up interconnects that connect GPU to GPU, and confining it, if it survived at all, to narrower memory expansion and pooling roles.

Nine months on, the narrower role is exactly where Samsung and SK hynix are building.

1. October 2025: SemiAnalysis publishes its verdict that CXL had been largely abandoned for AI infrastructure use.
2. June 2026: SK hynix shows a second generation, 256 gigabyte CMM-DDR5 module built on the CXL 3.2 standard at HPE’s Discover conference in Las Vegas, running inside a pooled memory server from AI infrastructure firm Liqid.
3. July 6, 2026: Industry sources tell trade outlet The Elec that Samsung has delayed mass production of its next generation, CXL 3.1 based CMM-D module.
4. July 9, 2026: Samsung discloses inference benchmark results showing its CXL memory pool holding up close to DRAM level performance.

Three days separate the delay report and the benchmark, a gap that captures the state of the bet as well as anything else.

The Rebuttal in Three Benchmarks

Samsung and SK hynix are not the only ones with numbers. Astera Labs, a Nasdaq listed chipmaker that builds connectivity hardware for AI data centers, ran its own demonstration with memory maker SMART Modular Technologies in September 2025, using its Leo CXL Smart Memory Controllers to add capacity for a large language model inference workload.

All three results came from the companies’ own testing under conditions they chose, which is a caveat worth holding onto. But three separate firms, testing three different pieces of hardware, arrived at results pointing the same direction. That is a harder pattern to wave away than a single number would be.

None of it makes CXL a replacement for HBM. HBM still does the heavy bandwidth work of feeding the compute engine during training and dense inference. What CXL adds is room, freeing the costlier, faster memory for the work that actually needs the speed. The catch is that CXL memory itself runs slower than local DRAM, so a lot of its value depends on software correctly deciding which data belongs on which tier, which is why controllers and firmware have become as competitive as the memory chips themselves.

Nvidia Hedges Its Bet With a Rival of Its Own

The clearest sign the CXL wager has legs is that Nvidia, the company with every incentive to keep AI data centers inside its own proprietary connections, is building CXL support into its next generation server CPU anyway.

Vera, Nvidia’s successor to its Grace data center processor, pairs 88 custom Olympus cores with a memory subsystem delivering 1.2 terabytes per second of bandwidth and up to 50 percent faster performance on agentic AI sandbox workloads, according to Nvidia’s own technical blog. Chip research firm Atlas Peak Research reports that Vera also supports PCIe Gen6 and the CXL 3.1 standard, giving data center operators an open path to add memory capacity instead of relying only on Nvidia’s proprietary links.

Nvidia is hedging even that bet, though. The company is also pushing its own Context Memory eXtension, or CMX, a proprietary offload layer aimed at the same overflowing inference cache that CXL targets, according to semiconductor analysts covering the launch. A chip that supports an open standard while its maker markets a closed alternative is not a full endorsement. It is Nvidia keeping both doors open.

Early Winners in the CXL Supply Chain

Samsung and SK hynix are not the only companies with money riding on this. A small supply chain has formed around making CXL actually usable, and some of it is already generating real, cited business.

• Astera Labs builds the Leo CXL Smart Memory Controllers that sit between a server and its CXL memory cards; the company says each controller adds up to 2 terabytes of memory, letting cloud providers scale total server memory more than 1.5 times over.
• Liqid is the AI infrastructure firm whose pooled memory server carried SK hynix’s CMM-DDR5 demonstration at HPE Discover, giving the memory maker a working system to show rather than a bare chip on a table.
• Microsoft Azure has already validated Astera’s controllers on its M series virtual machines, aimed squarely at memory hungry workloads like in memory databases, evidence that at least one hyperscaler is testing this beyond the lab.

None of these companies make the memory chips themselves. They make the plumbing around them, and plumbing businesses tend to arrive early, before anyone is certain the pipes will carry real volume.

Intel and AMD Are Holding Up Samsung’s Next Chip

Samsung has said that despite “some changes to parts of the plan,” it is preparing to begin CXL memory production on schedule. The company’s own framing plays down what industry sources describe more bluntly.

Samsung’s newest CXL memory module, built to the CXL 3.1 standard, was due to ship customer samples in June, according to trade publication The Elec. That schedule slipped, and Samsung is continuing to produce its current, CXL 2.0 based module in the meantime. The reason has nothing to do with Samsung’s own factories. “Neither Intel nor AMD has released a CPU supporting PCIe 6.0,” an industry source told the outlet, and CXL 3.1 cannot reach servers until Intel’s next Xeon platform, code named Diamond Rapids, and AMD’s next EPYC platform, code named Venice, actually ship. Intel had aimed to launch Diamond Rapids in the second half of 2026; that timeline has reportedly slipped into 2027.

That leaves Samsung’s most advanced memory product waiting on two rival companies’ chip roadmaps, a dependency the Korea Herald’s original reporting flagged when it noted the timeline could slip into 2027 as supporting server platforms run late. SK hynix has not set a production date at all for its 256 gigabyte, CXL 3.2 based module, which suggests it is watching the same processor calendar.

How Fast Will CXL Adoption Really Grow?

Not especially fast yet, based on the evidence so far. Research firm Yole Research estimated roughly two thirds of servers were already CXL capable in early 2025 and projects that share will top 90 percent by the end of 2026. But capable is not the same as deployed at scale, and the people closest to the market expect the real ramp to start only now.

“As AI expands, so will the market’s appetite for CXL, and that really takes off from 2026,” said Yim So-jung, an analyst at Seoul brokerage Eugene Investment & Securities. “By 2028, CXL-capable server platforms should be the mainstream.”

That timeline assumes Intel and AMD deliver the processors CXL 3.1 needs on something close to schedule. Whether Samsung and SK hynix ship on that timeline now rests on chips neither company builds.

Frequently Asked Questions

Does CXL Memory Already Work With Servers Sold Today?

Yes, in an earlier form. Samsung’s current CMM-D module uses the CXL 2.0 standard and runs on today’s Intel and AMD server chips, and the company is continuing to produce it while its newer CXL 3.1 module waits for next generation processors. It is only the newest, higher capacity generation of CXL memory that needs hardware, chiefly Intel’s Diamond Rapids and AMD’s Venice platforms, that has not shipped yet.

How Widely Adopted Is CXL Already, According to Researchers?

Semiconductor research firm Yole Research put roughly two thirds of servers at CXL capable status in early 2025 and expects that to exceed 90 percent by the end of 2026. That figure measures hardware support for the standard, not how many of those servers are actually running pooled or expanded CXL memory in production.

What Software Decides Which Data Sits in CXL Memory?

Controller and firmware makers handle that tiering. Astera Labs, for example, pairs its Leo CXL controllers with a software suite called COSMOS that manages link stability and performance monitoring across a fleet of servers, part of why memory management tools have become as competitive as the chips themselves.

What Is the Real Difference Between CXL Memory and HBM?

HBM sits directly on the same package as a GPU for maximum feed speed, while CXL memory connects over PCIe, a link whose data rate has grown roughly 16 times since 2019, from 32 gigabytes per second to 512 gigabytes per second, according to industry analysis, but which still trails HBM’s on package bandwidth. CXL trades some of that speed for far greater capacity, making it suited to holding overflow data like inference caches rather than feeding a chip directly.